Define layout ports and match them to the circuit

Before starting

Use the complete inline microstrip example to inspect the layout, process and circuit together. These are MQS inductance ports. EQS conductor labels and full impedance-port setups have separate rules; changing Mode alone does not convert them.

Steps

1. In process.ldf identify the actual material names and annotation IDs. The teaching example uses M1/M0 with TermLayer 19 and TextLayer 18.
2. Put one TERM path exactly on each intended strip edge: x = 0 and x = strip_length, each from y = strip_width to y = 0. Keep endpoints aligned with the conductor boundary.
3. Place a TEXT label on each edge midpoint. P1 M1 M0 means positive M1 and negative M0; P2 uses the same layer polarity at the other edge.
4. Match those labels to P1 1 0 and P2 2 0 in strip.cir. L1 connects nodes 1 and 2; node 0 is the common negative terminal.
5. Save all files, inspect the generated geometry/terminals and run the owning IXI project. Check the current terminal table rather than assuming that a visually nearby label was linked correctly.

Label and node mapping

Layout label     Positive layer   Negative layer   Netlist
P1 M1 M0         M1               M0               P1 1 0
P2 M1 M0         M1               M0               P2 2 0

Extracted branch: L1 1 2 3.9e-12
Geometry: x = 0 and x = %strip_length; label y = %strip_width/2

Geometry and polarity rules

For these line terminals the path centreline defines the connection. Width = 1 is a visual aid and does not replace the edge alignment or define an extra physical conductor. For GDS line terminals the manual recommends paths or two-point polygons rather than collapsed boxes.

TerminalInRange controls how a label position can be associated with the terminal object. Increasing it does not repair a wrong layer, an off-edge terminal or incorrect circuit topology.

Separate Pname+ and Pname- labels can define distributed positive and negative terminals. Virtual-cut ports and via/junction-derived terminals have additional geometry rules; do not substitute them into this edge-port example without reviewing the appropriate model.

Check the result

The checked run identifies p1+ and p2+ on M1 and p1- and p2- on M0, all as line/edge surfaces. The inline and maintained GDS examples produce identical mesh bytes and L1.

The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime.

The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change.

If the problem remains

Changing only the P2 layout label to P9 leaves a mismatched circuit port. The checked CLI rejects this case without an extracted L1; restoring P2 recovers the original result. Check the actual declared names, layer polarity, label coordinates and terminal edges before changing fitting settings.

The current candidate can flag TERM/TEXT with IXI_CROSS_UNKNOWN_LAYER even though these annotation aliases are accepted by the checked Core run and resolved to TermLayer/TextLayer. This focused mismatch is tracked as KB-GUI-005. Check the actual alias and declared layer numbers; do not rename conductor layers or ignore unrelated warnings.

If ports map correctly but fitted values seem surprising, inspect the actual branch topology, merged series branches and identifiability. A low algebraic residual does not prove correct geometry or physical calibration.

Actual GUI rejection and correction

Changing only the real Raw IXI label P2 to P9 and saving produced Failed - Invalid setup with a specific P2 diagnostic; TTH was not executed and that failed receipt had no extracted L1 row. Saving P2 again and using the production run action recovered the baseline.

The corrected run, Stop/retry and a rerun in a separate process recovered the same baseline at printed precision. A correct label name is only one part of the geometry, polarity and topology checks described above.