8 beta/preview
Package applicability is under review; follow the stated version and platform limits.
Before starting
This is an InductEx® extraction topology. Its P/J/B/I port identifiers describe excitation connections; do not paste a complete JoSIM device/transient deck into this file. Download the shared complete example for the matching process and layout.
Steps
- Create or open strip.cir as an InductEx® Netlist in Studio. Start any title with *; a bare SPICE title line is not the InductEx® title convention.
- Define each extracted branch with its element name and positive/negative node names. In this example L1 connects node 1 to node 2.
- Declare P1 1 0 and P2 2 0. Match P1/P2 to the layout labels and connect node 0 to the intended common negative terminal, here M0.
- Enter design values in the units specified by UnitL/UnitR in the process. Save strip.cir and confirm strip.ixi references it before running the project.
- Inspect current run status, recovered terminal mapping, requested branch names, units and fit/design diagnostics. Numerical fit quality is separate from whether the topology describes the real circuit.
Complete strip.cir
* Extraction topology, design inductance in henries because UnitL=1
L1 1 2 3.9e-12
P1 1 0
P2 2 0
.endRead the topology and design value
L1 1 2 3.9e-12 defines the branch model between the two strip ends; P1 and P2 return those ends to node 0 through the negative terminal. Node names describe abstract circuit connectivity and need not encode geometric positions.
With UnitL = 1 the design value is 3.9e-12 H. Design values are optional in the maintained format; omitting them removes that design comparison rather than defining a zero-inductance target.
For mutual terms K/M refer to inductor names rather than node names. Choose a topology that the available excitations can identify. Extra branches do not create independent information, and a negative fitted value is not automatically an invalid extraction. Use the dedicated modelling guides for fit interpretation.
Check the result
The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime.
The one-branch teaching example is not evidence that an arbitrary multi-branch circuit is identifiable or calibrated. Inspect fit rank and residuals along with geometry and excitation coverage.
The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change.
If the problem remains
An incomplete line such as L1 1 is rejected by the production editor analysis. Restore both terminal nodes before checking the design value. A P2/P9 mismatch between layout and netlist was rejected by the CLI and recovered after restoring the intended name.
NETLIST_UNSUPPORTED_DIRECTIVE on .end is a reproduced editor/CLI mismatch in this candidate (KB-EDITOR-001). The checked 8.0.1 CLI accepts this terminator and extracts the circuit. Inspect other warnings and the actual run outcome separately; an editor warning is not itself an extraction result.
For JoSIM handoff, use the current IXI back-annotation request and a separate simulation template. The historical netlist BACK-ANNOTATE location has a version-specific trap; follow the dedicated checked handoff guide.
Actual native result check
The native workflow opened and edited this complete circuit, ran the normal engine and recovered after correcting a P2/P9 mismatch in the layout labels. Match the current result units to UnitL; the netlist’s optional design value does not set an accuracy tolerance.
Sources and verification details
Recorded inputs/builds only. Complete walkthrough and final-package acceptance remain separate.
VAL-020 · Windows catalog InductEx® 8.0.1 (2 November 2026) and its bundled TTH 1.1.50; not final-package acceptance
Complete inline MQS strip, byte-identical mesh and identical inductance versus the maintained GDS example, length/display-unit changes, one mesh refinement and missing-process/port/layer rejection and recovery
Sixteen bounded CLI checks. One refinement observation is not a convergence threshold. Design agreement is not physical calibration or solver/fit residual acceptance. Native GUI authoring, cancellation/retry, restart and final distributed-package checks remain pending.
VAL-021 · Frozen current Windows Studio editor/nominal-process analysis source, 3 November 2026
Seventeen production-parser/analysis checks: exact input syntax, three-layer nominal stack/units, malformed input and restoration, plus focused reproduction of TERM/TEXT annotation alias warnings
This route is editor analysis only. It does not construct the Core model, run an extraction, verify physical calibration or complete a native GUI walkthrough. The accepted .end directive still receives an editor warning (KB-EDITOR-001); annotation alias warnings remain KB-GUI-005.
VAL-023 · Frozen Windows Studio source candidate with normal Core 8.0.1 dispatch, 3 November 2026; not a final distributed package
Normal production source edits/Undo/Redo/Save, licensed baseline/length/unit runs, port failure and correction, Stop/retry and a separate-process single-tab restart/rerun. File/directory selection used predetermined paths at the production dialog boundary
Eighteen independent checks cover these stated routes. The prior Completed label after a saved source edit remains KB-GUI-008; stale-state acceptance is not passed. A Cancelled receipt retained an L1 row and is not accepted as a completed solve. Physical pickers, complete GUI article, final distributed package, other platforms, physical accuracy and mesh convergence remain pending. KB-GUI-006 single-tab restart workaround remains separate.
studio-extraction-netlist
Current Windows Studio source, native authoring illustration, 3 November 2026
Authoring illustration only; no GUI extraction or complete walkthrough is shown. CLI/editor results are recorded separately. Annotation alias and .end warnings remain under review.
studio-inline-current-inductance
Frozen Windows Studio source candidate, actual native workflow, 3 November 2026
This image shows the stated recorded control/result only. The retained Completed-after-edit observation remains open; a Cancelled receipt is not accepted numerical success. Complete GUI article and final-package checks remain pending.
- inductex:docs/manual/ix_netlist.tex · Title/comments, elements, design values and ports; BACK-ANNOTATE limits remain separate
- inductex:docs/manual/ix_ports.tex · Layout terminal polarity matched to netlist nodes
- inductex:docs/manual/studio_projects.tex · Create/open a netlist and run its owning IXI project
- validation:inductex-inputs-windows-20261103 · VAL-020 licensed CLI and VAL-021 separate editor-analysis checks; exact scope retained
- capture:studio-inputs-20261103T163127 · Native authoring illustration only; exact reviewed input and image bytes
- validation:studio-inputs-native-windows-20261103 · VAL-023; actual native edits, numerical runs, port recovery, Stop/retry and separate-process single-tab restart; provenance limitation retained
- The five cited maintained references still match their reviewed inventory hashes; existing source baselines were preserved.
- VAL-023 adds eighteen independent native checks. The saved-source completion label is an open provenance observation (KB-GUI-008); the actual Cancelled verdict is kept distinct from retained numerical rows. Original input bytes were restored.
- VAL-020 CLI and VAL-021 editor analysis remain separate from the later normal native workflow. Complete physical pickers, article/release acceptance and numerical qualification remain pending.