{"sections":[{"heading":"Before starting","paragraphs":["This is an InductEx extraction topology. Its P/J/B/I port identifiers describe excitation connections; do not paste a complete JoSIM device/transient deck into this file. Download the shared complete example for the matching process and layout."]},{"figures":[{"asset_id":"studio-extraction-netlist","caption":"The complete L1/P1/P2 extraction netlist in the actual editor. The candidate’s .end warning is a reproduced diagnostic mismatch, explained below."}],"heading":"Steps","steps":["Create or open strip.cir as an InductEx Netlist in Studio. Start any title with *; a bare SPICE title line is not the InductEx title convention.","Define each extracted branch with its element name and positive/negative node names. In this example L1 connects node 1 to node 2.","Declare P1 1 0 and P2 2 0. Match P1/P2 to the layout labels and connect node 0 to the intended common negative terminal, here M0.","Enter design values in the units specified by UnitL/UnitR in the process. Save strip.cir and confirm strip.ixi references it before running the project.","Inspect current run status, recovered terminal mapping, requested branch names, units and fit/design diagnostics. Numerical fit quality is separate from whether the topology describes the real circuit."]},{"code":"* Extraction topology, design inductance in henries because UnitL=1\nL1 1 2 3.9e-12\nP1 1 0\nP2 2 0\n.end","heading":"Complete strip.cir"},{"heading":"Read the topology and design value","paragraphs":["L1 1 2 3.9e-12 defines the branch model between the two strip ends; P1 and P2 return those ends to node 0 through the negative terminal. Node names describe abstract circuit connectivity and need not encode geometric positions.","With UnitL = 1 the design value is 3.9e-12 H. Design values are optional in the maintained format; omitting them removes that design comparison rather than defining a zero-inductance target.","For mutual terms K/M refer to inductor names rather than node names. Choose a topology that the available excitations can identify. Extra branches do not create independent information, and a negative fitted value is not automatically an invalid extraction. Use the dedicated modelling guides for fit interpretation."]},{"heading":"Check the result","paragraphs":["The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime.","The one-branch teaching example is not evidence that an arbitrary multi-branch circuit is identifiable or calibrated. Inspect fit rank and residuals along with geometry and excitation coverage.","The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change."]},{"heading":"If the problem remains","paragraphs":["An incomplete line such as L1 1 is rejected by the production editor analysis. Restore both terminal nodes before checking the design value. A P2/P9 mismatch between layout and netlist was rejected by the CLI and recovered after restoring the intended name.","NETLIST_UNSUPPORTED_DIRECTIVE on .end is a reproduced editor/CLI mismatch in this candidate (KB-EDITOR-001). The checked 8.0.1 CLI accepts this terminator and extracts the circuit. Inspect other warnings and the actual run outcome separately; an editor warning is not itself an extraction result.","For JoSIM handoff, use the current IXI back-annotation request and a separate simulation template. The historical netlist BACK-ANNOTATE location has a version-specific trap; follow the dedicated checked handoff guide."]},{"figures":[{"asset_id":"studio-inline-current-inductance","caption":"Current native L1 result for this one-branch topology, with the original design and result values in H."}],"heading":"Actual native result check","paragraphs":["The native workflow opened and edited this complete circuit, ran the normal engine and recovered after correcting a P2/P9 mismatch in the layout labels. Match the current result units to UnitL; the netlist’s optional design value does not set an accuracy tolerance."]}],"canonical_url":"https://www.sun-magnetics.com/knowledge-base/inductex-netlist-build","url":"/knowledge-base/inductex-netlist-build","known_issues":[{"disposition":"supported_path","id":"KB-EDITOR-001","title":"Extraction netlist terminator receives an editor warning","public_notice":"The checked extraction netlist accepts .end while its editor reports this specific unsupported-directive warning. Preserve the complete input and check extraction independently; do not suppress unrelated warnings.","claim_scope":"Only the affected claim and recorded build/input; not whole-guide or final-release acceptance"},{"disposition":"verified_workaround","id":"KB-GUI-006","title":"Normal multi-tab exit saves the last tab as active","public_notice":"Save work and close other saved tabs before exit when the intended Studio project must return as active. The checked single-tab restart does not repair multi-tab selection.","claim_scope":"Only the affected claim and recorded build/input; not whole-guide or final-release acceptance"},{"disposition":"verified_workaround","id":"KB-GUI-008","title":"A saved source edit leaves the prior Completed result visible","public_notice":"After a source edit, save the intended inputs, choose Run again and verify the new result. An earlier Completed label may still refer to the previous generation.","claim_scope":"Only the affected claim and recorded build/input; not whole-guide or final-release acceptance"}],"search_record":{"execution":true,"relatedProducts":[],"version_tags":["InductEx 8 preview"],"text":"Build the circuit netlist required for extraction Describe the branch model and port-to-node topology that InductEx fits, with consistent design units and a complete microstrip netlist. InductEx 8 beta/preview How to circuit extraction netlist L1 P1 P2 node 0 SPICE title design value UnitL NETLIST_UNSUPPORTED_DIRECTIVE .end mutual inductor names Before starting This is an InductEx extraction topology. Its P/J/B/I port identifiers describe excitation connections; do not paste a complete JoSIM device/transient deck into this file. Download the shared complete example for the matching process and layout.  Steps Create or open strip.cir as an InductEx Netlist in Studio. Start any title with *; a bare SPICE title line is not the InductEx title convention. Define each extracted branch with its element name and positive/negative node names. In this example L1 connects node 1 to node 2. Declare P1 1 0 and P2 2 0. Match P1/P2 to the layout labels and connect node 0 to the intended common negative terminal, here M0. Enter design values in the units specified by UnitL/UnitR in the process. Save strip.cir and confirm strip.ixi references it before running the project. Inspect current run status, recovered terminal mapping, requested branch names, units and fit/design diagnostics. Numerical fit quality is separate from whether the topology describes the real circuit.  The complete L1/P1/P2 extraction netlist in the actual editor. The candidate’s .end warning is a reproduced diagnostic mismatch, explained below. The native extraction-netlist editor shows L1 between nodes 1 and 2 and ports P1 and P2 returning to node 0, with an editor warning on .end. Complete strip.cir * Extraction topology, design inductance in henries because UnitL=1\nL1 1 2 3.9e-12\nP1 1 0\nP2 2 0\n.end Read the topology and design value L1 1 2 3.9e-12 defines the branch model between the two strip ends; P1 and P2 return those ends to node 0 through the negative terminal. Node names describe abstract circuit connectivity and need not encode geometric positions. With UnitL = 1 the design value is 3.9e-12 H. Design values are optional in the maintained format; omitting them removes that design comparison rather than defining a zero-inductance target. For mutual terms K/M refer to inductor names rather than node names. Choose a topology that the available excitations can identify. Extra branches do not create independent information, and a negative fitted value is not automatically an invalid extraction. Use the dedicated modelling guides for fit interpretation.  Check the result The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime. The one-branch teaching example is not evidence that an arbitrary multi-branch circuit is identifiable or calibrated. Inspect fit rank and residuals along with geometry and excitation coverage. The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change.  If the problem remains An incomplete line such as L1 1 is rejected by the production editor analysis. Restore both terminal nodes before checking the design value. A P2/P9 mismatch between layout and netlist was rejected by the CLI and recovered after restoring the intended name. NETLIST_UNSUPPORTED_DIRECTIVE on .end is a reproduced editor/CLI mismatch in this candidate (KB-EDITOR-001). The checked 8.0.1 CLI accepts this terminator and extracts the circuit. Inspect other warnings and the actual run outcome separately; an editor warning is not itself an extraction result. For JoSIM handoff, use the current IXI back-annotation request and a separate simulation template. The historical netlist BACK-ANNOTATE location has a version-specific trap; follow the dedicated checked handoff guide.  Actual native result check The native workflow opened and edited this complete circuit, ran the normal engine and recovered after correcting a P2/P9 mismatch in the layout labels. Match the current result units to UnitL; the netlist’s optional design value does not set an accuracy tolerance.  Current native L1 result for this one-branch topology, with the original design and result values in H. Current native raw output gives the 100 micrometre strip L1 as 3.89648e-12 H against the 3.9e-12 H design value.","id":"inductex-netlist-build","keywords":"circuit extraction netlist L1 P1 P2 node 0 SPICE title design value UnitL NETLIST_UNSUPPORTED_DIRECTIVE .end mutual inductor names","kind":"How to","title":"Build the circuit netlist required for extraction","product":"InductEx"},"version":"8 beta/preview","id":"inductex-netlist-build","related":["/knowledge-base/inductex-ixi-geometry","/knowledge-base/inductex-process-build","/knowledge-base/inductex-port-design","/knowledge-base/cross-tool-extracted-circuit","/knowledge-base/inductex-completed-after-edit"],"downloads":[{"url":"/_functions/kbExample?name=inductex-inline-microstrip.zip","scope":"Exact checked input files plus instructions; final-release/platform applicability remains pending.","files":["strip.ixi","process.ldf","strip.cir","README.txt"],"id":"inductex-inline-microstrip","requires":["Matching licensed InductEx 8/TTH runtime","New writable directory; keep strip.ixi, process.ldf and strip.cir together","Review the stated Windows 8.0.1 scope; complete GUI/final-package acceptance remains pending"],"title":"Complete inline MQS microstrip inputs"}],"publication_status":"published","numerical_output":null,"provenance":{"execution_checks":[{"routes":["cli"],"scope":"Complete inline MQS strip, byte-identical mesh and identical inductance versus the maintained GDS example, length/display-unit changes, one mesh refinement and missing-process/port/layer rejection and recovery","result":"passed","articles":["inductex-ixi-geometry","inductex-process-build","inductex-netlist-build","inductex-port-design"],"purpose":"inductex-complete-inline-inputs-and-dependency-recovery","version":"Windows catalog InductEx 8.0.1 (2 November 2026) and its bundled TTH 1.1.50; not final-package acceptance","id":"VAL-020","records":["input-review","retained private process diagnostics","original input hashes"],"limit":"Sixteen bounded CLI checks. One refinement observation is not a convergence threshold. Design agreement is not physical calibration or solver/fit residual acceptance. Native GUI authoring, cancellation/retry, restart and final distributed-package checks remain pending.","observed":{"single_refinement_relative_change":0.006147298269211898,"refined_L1_H":3.872526244e-12,"exit_codes":{"layer-name-restored":0,"process-restored":0,"port-name-mismatch":1,"port-name-restored":0,"baseline":0,"refined-mesh":0,"layer-name-mismatch":1,"longer-strip":0,"missing-process":1,"picohenry-display":0},"picohenry_display_L1_pH":3.896479063,"longer_strip_L1_H":4.679059834e-12,"design_deviation_percent":-0.0902804358974274,"reference_L1_H":3.896479063e-12,"L1_H":3.896479063e-12}},{"routes":["editor-input-analysis"],"scope":"Seventeen production-parser/analysis checks: exact input syntax, three-layer nominal stack/units, malformed input and restoration, plus focused reproduction of TERM/TEXT annotation alias warnings","result":"passed","articles":["inductex-ixi-geometry","inductex-process-build","inductex-netlist-build","inductex-port-design"],"purpose":"inductex-production-editor-input-analysis","version":"Frozen current Windows Studio editor/nominal-process analysis source, 3 November 2026","id":"VAL-021","records":["editor-review","input hashes","selected production source hashes"],"limit":"This route is editor analysis only. It does not construct the Core model, run an extraction, verify physical calibration or complete a native GUI walkthrough. The accepted .end directive still receives an editor warning (KB-EDITOR-001); annotation alias warnings remain KB-GUI-005."},{"routes":["gui-native-scenario"],"scope":"Normal production source edits/Undo/Redo/Save, licensed baseline/length/unit runs, port failure and correction, Stop/retry and a separate-process single-tab restart/rerun. File/directory selection used predetermined paths at the production dialog boundary","result":"passed","articles":["inductex-ixi-geometry","inductex-process-build","inductex-netlist-build","inductex-port-design","inductex-read-results","inductex-completed-after-edit"],"prior_result_after_edit":{"status_after_saved_length_edit":"Completed","stale_state_accepted":false,"issue":"KB-GUI-008","source_has_length_120":true,"source_is_saved":true},"purpose":"studio-input-edit-run-recovery-cancel-restart","version":"Frozen Windows Studio source candidate with normal Core 8.0.1 dispatch, 3 November 2026; not a final distributed package","id":"VAL-023","cancellation":{"accepted_as_numerical_success":false,"normal_retry_passed":true,"raw_output_contains_inductance_row":true,"verdict":"Cancelled"},"records":["native-inputs","native-inputs-restart","independent-input-review","exact restored input hashes"],"limit":"Eighteen independent checks cover these stated routes. The prior Completed label after a saved source edit remains KB-GUI-008; stale-state acceptance is not passed. A Cancelled receipt retained an L1 row and is not accepted as a completed solve. Physical pickers, complete GUI article, final distributed package, other platforms, physical accuracy and mesh convergence remain pending. KB-GUI-006 single-tab restart workaround remains separate.","observed":{"port-recovery":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"baseline":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"restarted":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"longer":{"L1_H":4.67906e-12,"L1_display":4.67906e-12,"design_display":3.9e-12,"unit":"H"},"after-cancel":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"picohenry":{"L1_H":3.8964799999999996e-12,"L1_display":3.89648,"design_display":3.9,"unit":"pH"}}}],"figure_evidence":[{"evidence_limit":"Authoring illustration only; no GUI extraction or complete walkthrough is shown. CLI/editor results are recorded separately. Annotation alias and .end warnings remain under review.","id":"studio-extraction-netlist","reference_label":"Current Windows Studio source, native authoring illustration, 3 November 2026"},{"evidence_limit":"This image shows the stated recorded control/result only. The retained Completed-after-edit observation remains open; a Cancelled receipt is not accepted numerical success. Complete GUI article and final-package checks remain pending.","id":"studio-inline-current-inductance","reference_label":"Frozen Windows Studio source candidate, actual native workflow, 3 November 2026"}],"review_notes":["The five cited maintained references still match their reviewed inventory hashes; existing source baselines were preserved.","VAL-023 adds eighteen independent native checks. The saved-source completion label is an open provenance observation (KB-GUI-008); the actual Cancelled verdict is kept distinct from retained numerical rows. Original input bytes were restored.","VAL-020 CLI and VAL-021 editor analysis remain separate from the later normal native workflow. Complete physical pickers, article/release acceptance and numerical qualification remain pending."],"scope":"Recorded inputs/builds only. Complete walkthrough and final-package acceptance remain separate.","verification_requirements":{"gui_method":"product-native scenario or recorded operator walkthrough; relevant screenshots required","status":"review-incomplete","illustrations":"required","required":["technical-review","release-applicability","execution","recovery","numerical-interpretation","gui-workflow","illustrations"],"legacy_walkthrough_field":"pending retained; not a complete GUI article"},"sources":[{"id":"inductex:docs/manual/ix_netlist.tex","section":"Title/comments, elements, design values and ports; BACK-ANNOTATE limits remain separate"},{"id":"inductex:docs/manual/ix_ports.tex","section":"Layout terminal polarity matched to netlist nodes"},{"id":"inductex:docs/manual/studio_projects.tex","section":"Create/open a netlist and run its owning IXI project"},{"id":"validation:inductex-inputs-windows-20261103","section":"VAL-020 licensed CLI and VAL-021 separate editor-analysis checks; exact scope retained"},{"id":"capture:studio-inputs-20261103T163127","section":"Native authoring illustration only; exact reviewed input and image bytes"},{"id":"validation:studio-inputs-native-windows-20261103","section":"VAL-023; actual native edits, numerical runs, port recovery, Stop/retry and separate-process single-tab restart; provenance limitation retained"}]},"title":"Build the circuit netlist required for extraction","type":"How to","markdown_url":"/_functions/kbResource?path=markdown%2Finductex-netlist-build.md","summary":"Describe the branch model and port-to-node topology that InductEx® fits, with consistent design units and a complete microstrip netlist.","product":"InductEx"}