{"sections":[{"heading":"Before starting","paragraphs":["Use the complete inline microstrip example to inspect the layout, process and circuit together. These are MQS inductance ports. EQS conductor labels and full impedance-port setups have separate rules; changing Mode alone does not convert them."]},{"figures":[{"asset_id":"studio-inline-port-labels","caption":"Both edge paths and P1/P2 labels use the same geometry variables. Yellow annotation-layer warnings are retained; the checked Core mapping and diagnostic limit are explained below."}],"heading":"Steps","steps":["In process.ldf identify the actual material names and annotation IDs. The teaching example uses M1/M0 with TermLayer 19 and TextLayer 18.","Put one TERM path exactly on each intended strip edge: x = 0 and x = strip_length, each from y = strip_width to y = 0. Keep endpoints aligned with the conductor boundary.","Place a TEXT label on each edge midpoint. P1 M1 M0 means positive M1 and negative M0; P2 uses the same layer polarity at the other edge.","Match those labels to P1 1 0 and P2 2 0 in strip.cir. L1 connects nodes 1 and 2; node 0 is the common negative terminal.","Save all files, inspect the generated geometry/terminals and run the owning IXI project. Check the current terminal table rather than assuming that a visually nearby label was linked correctly."]},{"code":"Layout label     Positive layer   Negative layer   Netlist\nP1 M1 M0         M1               M0               P1 1 0\nP2 M1 M0         M1               M0               P2 2 0\n\nExtracted branch: L1 1 2 3.9e-12\nGeometry: x = 0 and x = %strip_length; label y = %strip_width/2","heading":"Label and node mapping"},{"heading":"Geometry and polarity rules","paragraphs":["For these line terminals the path centreline defines the connection. Width = 1 is a visual aid and does not replace the edge alignment or define an extra physical conductor. For GDS line terminals the manual recommends paths or two-point polygons rather than collapsed boxes.","TerminalInRange controls how a label position can be associated with the terminal object. Increasing it does not repair a wrong layer, an off-edge terminal or incorrect circuit topology.","Separate Pname+ and Pname- labels can define distributed positive and negative terminals. Virtual-cut ports and via/junction-derived terminals have additional geometry rules; do not substitute them into this edge-port example without reviewing the appropriate model."]},{"heading":"Check the result","paragraphs":["The checked run identifies p1+ and p2+ on M1 and p1- and p2- on M0, all as line/edge surfaces. The inline and maintained GDS examples produce identical mesh bytes and L1.","The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime.","The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change."]},{"heading":"If the problem remains","paragraphs":["Changing only the P2 layout label to P9 leaves a mismatched circuit port. The checked CLI rejects this case without an extracted L1; restoring P2 recovers the original result. Check the actual declared names, layer polarity, label coordinates and terminal edges before changing fitting settings.","The current candidate can flag TERM/TEXT with IXI_CROSS_UNKNOWN_LAYER even though these annotation aliases are accepted by the checked Core run and resolved to TermLayer/TextLayer. This focused mismatch is tracked as KB-GUI-005. Check the actual alias and declared layer numbers; do not rename conductor layers or ignore unrelated warnings.","If ports map correctly but fitted values seem surprising, inspect the actual branch topology, merged series branches and identifiability. A low algebraic residual does not prove correct geometry or physical calibration."]},{"figures":[{"asset_id":"studio-inline-current-inductance","caption":"The actual current native result after the intended P1/P2 model is run. The failed-port diagnostic was independently checked; this figure shows a successful numerical result."}],"heading":"Actual GUI rejection and correction","paragraphs":["Changing only the real Raw IXI label P2 to P9 and saving produced Failed - Invalid setup with a specific P2 diagnostic; TTH was not executed and that failed receipt had no extracted L1 row. Saving P2 again and using the production run action recovered the baseline.","The corrected run, Stop/retry and a rerun in a separate process recovered the same baseline at printed precision. A correct label name is only one part of the geometry, polarity and topology checks described above."]}],"canonical_url":"https://www.sun-magnetics.com/knowledge-base/inductex-port-design","url":"/knowledge-base/inductex-port-design","known_issues":[{"disposition":"supported_path","id":"KB-GUI-005","title":"Review annotation-layer warnings in the supplied inline example","public_notice":"Retain the specific annotation-alias warnings and check the process and terminal declarations. Do not change physical inputs merely to clear a warning; this mismatch does not invalidate every extraction.","claim_scope":"Only the affected claim and recorded build/input; not whole-guide or final-release acceptance"},{"disposition":"verified_workaround","id":"KB-GUI-006","title":"Normal multi-tab exit saves the last tab as active","public_notice":"Save work and close other saved tabs before exit when the intended Studio project must return as active. The checked single-tab restart does not repair multi-tab selection.","claim_scope":"Only the affected claim and recorded build/input; not whole-guide or final-release acceptance"},{"disposition":"verified_workaround","id":"KB-GUI-008","title":"A saved source edit leaves the prior Completed result visible","public_notice":"After a source edit, save the intended inputs, choose Run again and verify the new result. An earlier Completed label may still refer to the previous generation.","claim_scope":"Only the affected claim and recorded build/input; not whole-guide or final-release acceptance"}],"search_record":{"execution":true,"relatedProducts":[],"version_tags":["InductEx 8 preview"],"text":"Define layout ports and match them to the circuit Connect each named port to its positive/negative material layers, an actual terminal edge and the corresponding circuit nodes. InductEx 8 beta/preview How to P1 M1 M0 P2 missing TERM TEXT IXI_CROSS_UNKNOWN_LAYER port label terminal node mapping positive negative polarity TerminalInRange edge path Before starting Use the complete inline microstrip example to inspect the layout, process and circuit together. These are MQS inductance ports. EQS conductor labels and full impedance-port setups have separate rules; changing Mode alone does not convert them.  Steps In process.ldf identify the actual material names and annotation IDs. The teaching example uses M1/M0 with TermLayer 19 and TextLayer 18. Put one TERM path exactly on each intended strip edge: x = 0 and x = strip_length, each from y = strip_width to y = 0. Keep endpoints aligned with the conductor boundary. Place a TEXT label on each edge midpoint. P1 M1 M0 means positive M1 and negative M0; P2 uses the same layer polarity at the other edge. Match those labels to P1 1 0 and P2 2 0 in strip.cir. L1 connects nodes 1 and 2; node 0 is the common negative terminal. Save all files, inspect the generated geometry/terminals and run the owning IXI project. Check the current terminal table rather than assuming that a visually nearby label was linked correctly.  Both edge paths and P1/P2 labels use the same geometry variables. Yellow annotation-layer warnings are retained; the checked Core mapping and diagnostic limit are explained below. Raw IXI shows both TERM edge paths and the P1 M1 M0 and P2 M1 M0 labels at the midpoint of each edge. Label and node mapping Layout label     Positive layer   Negative layer   Netlist\nP1 M1 M0         M1               M0               P1 1 0\nP2 M1 M0         M1               M0               P2 2 0\n\nExtracted branch: L1 1 2 3.9e-12\nGeometry: x = 0 and x = %strip_length; label y = %strip_width/2 Geometry and polarity rules For these line terminals the path centreline defines the connection. Width = 1 is a visual aid and does not replace the edge alignment or define an extra physical conductor. For GDS line terminals the manual recommends paths or two-point polygons rather than collapsed boxes. TerminalInRange controls how a label position can be associated with the terminal object. Increasing it does not repair a wrong layer, an off-edge terminal or incorrect circuit topology. Separate Pname+ and Pname- labels can define distributed positive and negative terminals. Virtual-cut ports and via/junction-derived terminals have additional geometry rules; do not substitute them into this edge-port example without reviewing the appropriate model.  Check the result The checked run identifies p1+ and p2+ on M1 and p1- and p2- on M0, all as line/edge surfaces. The inline and maintained GDS examples produce identical mesh bytes and L1. The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime. The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change.  If the problem remains Changing only the P2 layout label to P9 leaves a mismatched circuit port. The checked CLI rejects this case without an extracted L1; restoring P2 recovers the original result. Check the actual declared names, layer polarity, label coordinates and terminal edges before changing fitting settings. The current candidate can flag TERM/TEXT with IXI_CROSS_UNKNOWN_LAYER even though these annotation aliases are accepted by the checked Core run and resolved to TermLayer/TextLayer. This focused mismatch is tracked as KB-GUI-005. Check the actual alias and declared layer numbers; do not rename conductor layers or ignore unrelated warnings. If ports map correctly but fitted values seem surprising, inspect the actual branch topology, merged series branches and identifiability. A low algebraic residual does not prove correct geometry or physical calibration.  Actual GUI rejection and correction Changing only the real Raw IXI label P2 to P9 and saving produced Failed - Invalid setup with a specific P2 diagnostic; TTH was not executed and that failed receipt had no extracted L1 row. Saving P2 again and using the production run action recovered the baseline. The corrected run, Stop/retry and a rerun in a separate process recovered the same baseline at printed precision. A correct label name is only one part of the geometry, polarity and topology checks described above.  The actual current native result after the intended P1/P2 model is run. The failed-port diagnostic was independently checked; this figure shows a successful numerical result. Current native raw output gives the 100 micrometre strip L1 as 3.89648e-12 H against the 3.9e-12 H design value.","id":"inductex-port-design","keywords":"P1 M1 M0 P2 missing TERM TEXT IXI_CROSS_UNKNOWN_LAYER port label terminal node mapping positive negative polarity TerminalInRange edge path","kind":"How to","title":"Define layout ports and match them to the circuit","product":"InductEx"},"version":"8 beta/preview","id":"inductex-port-design","related":["/knowledge-base/inductex-ixi-geometry","/knowledge-base/inductex-process-build","/knowledge-base/inductex-netlist-build","/knowledge-base/inductex-label-hierarchy","/knowledge-base/inductex-terminal-geometry","/knowledge-base/inductex-completed-after-edit"],"downloads":[{"url":"/_functions/kbExample?name=inductex-inline-microstrip.zip","scope":"Exact checked input files plus instructions; final-release/platform applicability remains pending.","files":["strip.ixi","process.ldf","strip.cir","README.txt"],"id":"inductex-inline-microstrip","requires":["Matching licensed InductEx 8/TTH runtime","New writable directory; keep strip.ixi, process.ldf and strip.cir together","Review the stated Windows 8.0.1 scope; complete GUI/final-package acceptance remains pending"],"title":"Complete inline MQS microstrip inputs"}],"publication_status":"published","numerical_output":null,"provenance":{"execution_checks":[{"routes":["cli"],"scope":"Complete inline MQS strip, byte-identical mesh and identical inductance versus the maintained GDS example, length/display-unit changes, one mesh refinement and missing-process/port/layer rejection and recovery","result":"passed","articles":["inductex-ixi-geometry","inductex-process-build","inductex-netlist-build","inductex-port-design"],"purpose":"inductex-complete-inline-inputs-and-dependency-recovery","version":"Windows catalog InductEx 8.0.1 (2 November 2026) and its bundled TTH 1.1.50; not final-package acceptance","id":"VAL-020","records":["input-review","retained private process diagnostics","original input hashes"],"limit":"Sixteen bounded CLI checks. One refinement observation is not a convergence threshold. Design agreement is not physical calibration or solver/fit residual acceptance. Native GUI authoring, cancellation/retry, restart and final distributed-package checks remain pending.","observed":{"single_refinement_relative_change":0.006147298269211898,"refined_L1_H":3.872526244e-12,"exit_codes":{"layer-name-restored":0,"process-restored":0,"port-name-mismatch":1,"port-name-restored":0,"baseline":0,"refined-mesh":0,"layer-name-mismatch":1,"longer-strip":0,"missing-process":1,"picohenry-display":0},"picohenry_display_L1_pH":3.896479063,"longer_strip_L1_H":4.679059834e-12,"design_deviation_percent":-0.0902804358974274,"reference_L1_H":3.896479063e-12,"L1_H":3.896479063e-12}},{"routes":["editor-input-analysis"],"scope":"Seventeen production-parser/analysis checks: exact input syntax, three-layer nominal stack/units, malformed input and restoration, plus focused reproduction of TERM/TEXT annotation alias warnings","result":"passed","articles":["inductex-ixi-geometry","inductex-process-build","inductex-netlist-build","inductex-port-design"],"purpose":"inductex-production-editor-input-analysis","version":"Frozen current Windows Studio editor/nominal-process analysis source, 3 November 2026","id":"VAL-021","records":["editor-review","input hashes","selected production source hashes"],"limit":"This route is editor analysis only. It does not construct the Core model, run an extraction, verify physical calibration or complete a native GUI walkthrough. The accepted .end directive still receives an editor warning (KB-EDITOR-001); annotation alias warnings remain KB-GUI-005."},{"routes":["gui-native-scenario"],"scope":"Normal production source edits/Undo/Redo/Save, licensed baseline/length/unit runs, port failure and correction, Stop/retry and a separate-process single-tab restart/rerun. File/directory selection used predetermined paths at the production dialog boundary","result":"passed","articles":["inductex-ixi-geometry","inductex-process-build","inductex-netlist-build","inductex-port-design","inductex-read-results","inductex-completed-after-edit"],"prior_result_after_edit":{"status_after_saved_length_edit":"Completed","stale_state_accepted":false,"issue":"KB-GUI-008","source_has_length_120":true,"source_is_saved":true},"purpose":"studio-input-edit-run-recovery-cancel-restart","version":"Frozen Windows Studio source candidate with normal Core 8.0.1 dispatch, 3 November 2026; not a final distributed package","id":"VAL-023","cancellation":{"accepted_as_numerical_success":false,"normal_retry_passed":true,"raw_output_contains_inductance_row":true,"verdict":"Cancelled"},"records":["native-inputs","native-inputs-restart","independent-input-review","exact restored input hashes"],"limit":"Eighteen independent checks cover these stated routes. The prior Completed label after a saved source edit remains KB-GUI-008; stale-state acceptance is not passed. A Cancelled receipt retained an L1 row and is not accepted as a completed solve. Physical pickers, complete GUI article, final distributed package, other platforms, physical accuracy and mesh convergence remain pending. KB-GUI-006 single-tab restart workaround remains separate.","observed":{"port-recovery":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"baseline":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"restarted":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"longer":{"L1_H":4.67906e-12,"L1_display":4.67906e-12,"design_display":3.9e-12,"unit":"H"},"after-cancel":{"L1_H":3.89648e-12,"L1_display":3.89648e-12,"design_display":3.9e-12,"unit":"H"},"picohenry":{"L1_H":3.8964799999999996e-12,"L1_display":3.89648,"design_display":3.9,"unit":"pH"}}}],"figure_evidence":[{"evidence_limit":"Authoring illustration only; no GUI extraction or complete walkthrough is shown. CLI/editor results are recorded separately. Annotation alias and .end warnings remain under review.","id":"studio-inline-port-labels","reference_label":"Current Windows Studio source, native authoring illustration, 3 November 2026"},{"evidence_limit":"This image shows the stated recorded control/result only. The retained Completed-after-edit observation remains open; a Cancelled receipt is not accepted numerical success. Complete GUI article and final-package checks remain pending.","id":"studio-inline-current-inductance","reference_label":"Frozen Windows Studio source candidate, actual native workflow, 3 November 2026"}],"review_notes":["The five cited maintained references still match their reviewed inventory hashes; existing source baselines were preserved.","VAL-023 adds eighteen independent native checks. The saved-source completion label is an open provenance observation (KB-GUI-008); the actual Cancelled verdict is kept distinct from retained numerical rows. Original input bytes were restored.","VAL-020 CLI and VAL-021 editor analysis remain separate from the later normal native workflow. Complete physical pickers, article/release acceptance and numerical qualification remain pending."],"scope":"Recorded inputs/builds only. Complete walkthrough and final-package acceptance remain separate.","verification_requirements":{"gui_method":"product-native scenario or recorded operator walkthrough; relevant screenshots required","status":"review-incomplete","illustrations":"required","required":["technical-review","release-applicability","execution","recovery","numerical-interpretation","gui-workflow","illustrations"],"legacy_walkthrough_field":"pending retained; not a complete GUI article"},"sources":[{"id":"inductex:docs/manual/ix_ports.tex","section":"Inductance port definition, terminal geometry, layout labels and polarity"},{"id":"inductex:docs/manual/ix_netlist.tex","section":"Port names and positive/negative circuit nodes"},{"id":"inductex:docs/manual/ix_ldf.tex","section":"TermLayer/TextLayer and TerminalInRange"},{"id":"inductex:docs/manual/studio_projects.tex","section":"Inspect current project inputs and run/diagnostic results"},{"id":"validation:inductex-inputs-windows-20261103","section":"VAL-020 licensed CLI and VAL-021 separate editor-analysis checks; exact scope retained"},{"id":"capture:studio-inputs-20261103T163127","section":"Native authoring illustration only; exact reviewed input and image bytes"},{"id":"validation:studio-inputs-native-windows-20261103","section":"VAL-023; actual native edits, numerical runs, port recovery, Stop/retry and separate-process single-tab restart; provenance limitation retained"}]},"title":"Define layout ports and match them to the circuit","type":"How to","markdown_url":"/_functions/kbResource?path=markdown%2Finductex-port-design.md","summary":"Connect each named port to its positive/negative material layers, an actual terminal edge and the corresponding circuit nodes.","product":"InductEx"}