Choose and refine simulation and output time steps

Keep integration and output sampling distinct

For the fixed-step example, time_step controls integration and print_step sets the requested output cadence. print_start_time hides earlier waveform output. Omitting print_step emits accepted simulation samples; an explicit print_step must be positive.

The optional startup/initial-condition flags have separate meanings. Keep those settings and the circuit fixed during refinement. Adaptive stepping has additional controls and supported-analysis restrictions; this example checks fixed-step VOLTAGE/BDF only.

.TRAN time_step stop_time [print_start_time] [print_step] [UIC] [STARTUP|DST]

Create a common-grid RC comparison

Save the complete RC deck below as rc_coarse.cir. Copy it to rc_medium.cir and rc_fine.cir; change only the first .TRAN argument to 0.25p and 0.125p respectively. Keep stop time 100p, print start 0 and print step 2p in all three.

* RC response: 50 ohm, 0.2 pF, 10 ps time constant
.PARAM DRIVE=1m
V1 IN 0 PWL(0 0 10p 0 20p DRIVE 100p DRIVE)
R1 IN OUT 50
C1 OUT 0 0.2p
.OPTION ANALYSIS=VOLTAGE INTEGRATION=BDF
.TRAN 0.5p 100p 0 2p
.PRINT V(IN) V(OUT) I(R1)
.END

Run to three separate outputs

1. Confirm each run succeeds and each CSV is new.
2. Compare V(OUT) at the common output times and check peak values, threshold times or other required measurements. Keep units and source amplitude consistent.
3. Compare with the independent RC expression in the netlist guide. For this check the error window is 24–80 ps, away from the input-ramp corners.

josim-pro-cli -o rc_coarse.csv rc_coarse.cir
josim-pro-cli -o rc_medium.csv rc_medium.cir
josim-pro-cli -o rc_fine.csv rc_fine.cir

Interpret the checked refinement

All three checked CSV files contain 51 samples over 0–100 ps because the output cadence is 2 ps. The integration steps differ even though the output row counts match.

Maximum absolute V(OUT) error in the declared window fell from approximately 0.3607 microvolt at 0.5 ps to 0.0860 microvolt at 0.25 ps and 0.0210 microvolt at 0.125 ps. The comparison is against this ideal RC reference, not against another run treated as ground truth.

For a real circuit, set tolerances on its actual outputs or measured quantities, refine until those criteria and relevant model/reference checks are met, and record the remaining error. Preserve physical-model, startup, seed and stimulus settings. Do not transfer this RC result or its tolerance to a Josephson, noisy or transmission-line circuit.

Recover from an invalid output step

An explicit zero print_step was rejected without CSV in the checked runtime. Remove that optional argument to emit accepted steps, or supply a positive cadence and rerun to a fresh filename.

If refinements disagree, inspect discontinuities, analysis/integration mode, initial conditions, model validity and output interpolation. Increasing file precision or decreasing print_step alone does not resolve integration error.