Resources

Documents, software and libraries available for download
Our products

Install Files

 

Install files available for download.

Filename Size Last Modification
InductEx v6.0 Windows 45 MB 17 June 2020
InductEx v6.0 Linux 39 MB 17 June 2020
InductEx v6.0 Mac OS X 40 MB 17 June 2020

 

Resources

 

Documents available for download.

Filename Size Last Modification
Inductex v6.0 User Manual 38887 kB 17 June 2020
InductEx v4.30 User Manual 742 kB 14 March 2015

 

Process Data

Layer definition files for supported integrated circuit fabrication processes are listed on this page. If you need to model a new process, start from one of these files as an example, or contact us to do it for you.

MIT-LL 10 kA/cm2 Nb SFQ processes

(MIT Lincoln Laboratory, Lexington MA)

MITLL process data are not open to the general public. E-mail the SUN Magnetics team to request access.

 

Filename Description Last Modification
mitll_sfq5ee.ldf Layer definition file for MIT-LL SFQ5ee – CALIBRATED 6 Jun 2020
mitll_sfq5ee_res.ldf Layer definition file for MIT-LL SFQ5ee process with resistance – CALIBRATED 6 June 2020
mitll_sfq5ee_2019.ldf Layer definition file for MIT-LL SFQ4ee and SFQ5ee processes – CALIBRATED 25 Feb 2019
mitll_sfq5ee_resistance.ldf Layer definition file for MIT-LL SFQ4ee and SFQ5ee processes – no calibration 30 May 2019

 

Hypres 4.5 kA/cm2 Nb process

(Hypres, Inc., New York)

 

Filename Description Last Modification
h4k5.ldf Generic layer definitions (nominal process parameters) 18 February 2014
h4k5_fast.ldf Layer definitions for faster simulations 18 February 2014
h4k5_ma.ldf Layer definitions calibrated for Mask Aligner process 10 August 2013
h4k5_ws.ldf Layer definitions calibrated for Wafer Stepper process 18 February 2014
h4k5_res.ldf Generic layer definitions (nominal process parameters) with R2 layer resistors modelled 18 February 2014

 

FLUXONICS RSFQ1F 1 kA/cm2 Nb process

(IPHT Jena, Germany)

 

Filename Description Last Modification
i1k.ldf Generic layer definitions 10 August 2013
i1k_fast.ldf Layer definitions for faster simulations 10 August 2013
i1k_res.ldf Generic layer definitions with R1 layer resistors modelled 10 August 2013

 

OLD FLUXONICS RSFQ1D 1 kA/cm2 Nb process

(For calculations on layouts before 2012)

 

Filename Description Last Modification
i1k_old.ldf Generic layer definitions 10 August 2013
i1k_old_fast.ldf Layer definitions for faster simulations 10 August 2013

 

AIST STP2 and ADP2 processes

Click here for the AIST STP2 and ADP2 layer definition files.

Filename Description Last Modification
adp.ldf Layer info for AIST ADP Process (10kA/cm2) 18 February 2014
adp_fast.ldf Layer info for AIST ADP Process (10kA/cm2) 18 February 2014
stp_nores.ldf Layer info for AIST STP2 Process (2.5kA/cm2) 9 November 2015
stp_nores_fast.ldf Layer info for AIST STP2 Process (2.5kA/cm2) 23 November 2015
stp_nores_med.ldf Layer info for AIST STP2 Process (2.5kA/cm2) 23 November 2015
stp_res.ldf Layer info for AIST STP2 Process (2.5kA/cm2) 9 November 2015

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Publications

Journal publications about InductEx, or with results generated by InductEx, are listed below. Copyright remains with the respective journals. Final preprints (as accepted) can be downloaded directly.

Stellenbosch University publications about InductEx

Fourie CJ, and Jackman K 2019 Software tools for flux trapping and magnetic field analysis in superconducting circuits IEEE Trans. Appl. Supercond. 29 1301004
Jackman K, and Fourie CJ 2019 Multipole accelerated magnetic field calculations for superconducting circuits Supercond. Sci. Technol. 32 015011
Fourie CJ, Shawawreh C, Verink IV, and Filippov TV 2017 High accuracy InductEx calibration sets for MIT-LL SFQ4ee and SFQ5ee processes ​IEEE Trans. Appl. Supercond. 27​ 1300805
Jackman K, and Fourie CJ 2017 Flux trapping analysis in superconducting circuits IEEE Trans. Appl. Supercond. 27 ​1300105
Jackman K, and Fourie CJ 2016 Tetrahedral modelling method for inductance extraction of complex 3D superconducting structures ​IEEE Trans. Appl. Supercond. 26 ​0602305
Fourie CJ, Takeuchi N, and Yoshikawa N 2016 Inductance and current distribution extraction in Nb multilayer circuits with superconductive and resistive components ​IEICE Trans. Electron. ​E99-C​ 683-91
Fourie CJ 2015 Full-gate verification of superconductive integrated circuit layouts with InductEx IEEE Trans. Appl. Supercond. 25 1300209
Fourie CJ 2013 Calibration of inductance calculations to measurement data for superconductive integrated circuit processes IEEE Trans. Appl.
Supercond
. 23 1301305
Fourie CJ, Wetzstein O, Kunert J, and Meyer H-G 2013 SFQ circuits with ground plane hole-assisted inductive coupling designed with InductEx IEEE Trans. Appl. Supercond. 23 1300705
Fourie CJ, Wetzstein O, Kunert J, Toepfer H and Meyer H-G 2013 Experimentally verified inductance extraction and parameter study for superconductive integrated circuit wires crossing ground plane holes Supercond. Sci. Technol. 26 015016
Fourie CJ, Wetzstein O, Ortlepp T and Kunert J 2011 Three-dimensional multi-terminal superconductive integrated circuit inductance extraction Supercond. Sci. Technol. 24 125015

Collaborative publications that use or reference InductEx

Fourie CJ, Peng X, Numaguchi R and Yoshikawa N 2015 Inductance and coupling of stacked vias in a multilayer superconductive IC process IEEE Trans. Appl. Supercond. 25 1101104
Fourie CJ, Takahashi A and Yoshikawa N 2015 Fast and accurate inductance and coupling calculation for a multi-layer Nb process Supercond. Sci. Technol. 28 035013
Vernik IV, Kaplan S, Volkmann MH, Dotsenko A, Fourie CJ and. Mukhanov OA 2014 Design and Test of asynchronous eSFQ circuits Supercond. Sci. Technol. 27 044030
Anton SM, Sognnaes IAB, Birenbaum JS, O’Kelly SR, Fourie CJ and Clarke J 2013 Mean square flux noise in SQUIDs and qubits: numerical calculations Supercond. Sci. Technol. 26 075022
Volkmann MH, Sahu A, Fourie CJ and Mukhanov OA 2013 Implementation of energy efficient single flux quantum digital circuits with sub-aJ/bit operation Supercond. Sci. Technol. 26 015002
Wolf T, Bergeal N, Lesueur J, Fourie CJ, Faini G, Ulysse C and Febvre P 2013 YBCO Josephson junctions and striplines for RSFQ circuits made by ion irradiation IEEE Trans. Appl. Supercond. 23 1101205

Other publications that use or reference InductEx

Kempf S, Ferring A, Fleischmann A and Enss C 2015 Direct-current superconducting quantum interference devices for the readout of metallic magnetic calorimeters Supercond. Sci. Technol. 28 045008
Khapaev MM and Kupriyanov M Yu 2015 Inductance extraction of superconductor structures with internal current sources Supercond. Sci. Technol. 28 055013
Inoue K, Takeuchi N, Narama T, Yamanashi Y and Yoshikawa N 2015 Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields Supercond. Sci. Technol. 28 045020
Takeuchi N, Yamanashi Y and Yoshikawa N 2015 Adiabatic quantum-flux-parametron cell library adopting minimalist design J. Appl. Phys. 117 173912
Semenov VK, Polyakov YA and Tolpygo SK 2015 New ac-powered SFQ digital circuits IEEE Trans. Appl. Supercond. 25 1301507
Sato K, Yamanashi Y and Yoshikawa N 2015 High-speed operation of a Single Flux Quantum multiple input merger using a magnetically coupled SQUID stack IEEE Trans. Appl. Supercond. 25 1301605
Tolpygo SK, Bolkhovsky V, Weir TJ, Galbraith CJ, Johnson LM, Gouker MA and Semenov VK 2015 Inductance of circuit structures for MIT LL superconductor electronics fabrication process with 8 niobium layers IEEE Trans. Appl. Superconduct. 25 1100905
Takeuchi N, Ortlepp T, Yamanashi Y and Yoshikawa N 2015 Experimental demonstration of quantum-flux-latch-based circuits IEEE Trans. Appl. Supercond. 25 1300803
Takeuchi N, Ortlepp T, Yamanashi Y and Yoshikawa N 2014 Novel latch for adiabatic quantum-flux-parametron logic J. Appl. Phys. 115 103910
Takeuch N, Ortlepp T, Yamanashi Y and Yoshikawa N 2014 High-speed experimental demonstration of adiabatic quantum-flux-parametron gates using quantum-flux-latches IEEE Trans. Appl. Superconduct. 24 1300204
Collot R, Febvre P, Kunert J and Meyer H-G 2013 Operation of Low-Tc circuits in a magnetic environment IEEE Trans. Appl. Supercond. 23 1700404
Haverkamp I, Wetzstein O, Kunert J, Ortlepp T, Stolz R, Meyer H-G and Toepfer H 2012 Optimization of a digital SQUID magnetometer in terms of noise and distortion Supercond. Sci. Technol. 25 065012

 

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Free tools

This page hosts free software tools in a convenient repository.

JSIM and JSIM_n: console applications for Josephson circuit simulation. Fast and light-weight.

JSIM and the noise-enabled JSIM_n are ubiquitous Josephson circuit simulators; faster than Spice with inherent support for the Josephson junction.

The source code with makefile is included as a tar.gz archive, and is easy to build on Linux and Mac platforms.

The original paper on JSIM is also included because it is very difficult to find. It should be referenced as: E. S. Fang and T. Van Duzer, “A Josephson integrated circuit simulator (JSIM) for superconductive electronics application,” in Extended Abstracts of 1989 Intl. Superconductivity Electronics Conf. (ISEC ’89), Tokyo, Japan: JSAP, 1989, pp. 407-410.

Attachment Size
Windows executables for JSIM and JSIM_n 122.02 KB
JSIM user manual from Savoie University. (c) Pascal Febvre. 866.23 KB
JSIM_n source code, last modified by Mark Volkmann, 2014 124.15 KB
Original JSIM paper in Extended Abstracts of ISEC’89, by Emerson Fang 124.15 KB

Cell libraries

This page links to cell library repositories.

The FLUXONICS cell library houses GDS layout files, JSIM netlists, InductEx extraction batch files and more for every cell.

An experimental RSFQ cell library for the MITLL SFQ5ee process contains cells with integrated PTL drivers and receivers.

Open-source modules

This page contains the links to open-source repositories for superconducting EDA modules.

TimEx

TimEx is a netlist-to-Verilog HDL extraction module that finds timing parameters of SFQ circuits. The GitHub repository is https://github.com/sunmagnetics/TimEx​

​TimEx development was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office grant W911NF-17-1-0120.

JoSIM

JoSIM is an open-source simulation engine for superconducting circuits. It combines the functionality of JSIM and WRSpice. The GitHub repository is https://github.com/JoeyDelp/JoSIM​

​JoSIM development was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office grant W911NF-17-1-0120.

AUTO

AUTO is a suite of modules for SFQ circuit margin and yield analysis and optimization. The GitHub repository is https://github.com/coldlogix/auto

AUTO was developed primarily by Thomas Ortlepp at Ilmenau University of Technology.