Layer definition files for supported integrated circuit fabrication processes are listed on this page. If you need to model a new process, start from one of these files as an example, or contact us to do it for you.
MIT-LL 10 kA/cm2 Nb SFQ processes
(MIT Lincoln Laboratory, Lexington MA)
MITLL process data are not open to the general public. E-mail the SUN Magnetics team to request access.
|mitll_sfq5ee.ldf||Layer definition file for MIT-LL SFQ5ee – CALIBRATED||6 Jun 2020|
|mitll_sfq5ee_res.ldf||Layer definition file for MIT-LL SFQ5ee process with resistance – CALIBRATED||6 June 2020|
|mitll_sfq5ee_2019.ldf||Layer definition file for MIT-LL SFQ4ee and SFQ5ee processes – CALIBRATED||25 Feb 2019|
|mitll_sfq5ee_resistance.ldf||Layer definition file for MIT-LL SFQ4ee and SFQ5ee processes – no calibration||30 May 2019|
Hypres 4.5 kA/cm2 Nb process
(Hypres, Inc., New York)
|h4k5.ldf||Generic layer definitions (nominal process parameters)||18 February 2014|
|h4k5_fast.ldf||Layer definitions for faster simulations||18 February 2014|
|h4k5_ma.ldf||Layer definitions calibrated for Mask Aligner process||10 August 2013|
|h4k5_ws.ldf||Layer definitions calibrated for Wafer Stepper process||18 February 2014|
|h4k5_res.ldf||Generic layer definitions (nominal process parameters) with R2 layer resistors modelled||18 February 2014|
FLUXONICS RSFQ1F 1 kA/cm2 Nb process
(IPHT Jena, Germany)
|i1k.ldf||Generic layer definitions||10 August 2013|
|i1k_fast.ldf||Layer definitions for faster simulations||10 August 2013|
|i1k_res.ldf||Generic layer definitions with R1 layer resistors modelled||10 August 2013|
OLD FLUXONICS RSFQ1D 1 kA/cm2 Nb process
(For calculations on layouts before 2012)
|i1k_old.ldf||Generic layer definitions||10 August 2013|
|i1k_old_fast.ldf||Layer definitions for faster simulations||10 August 2013|
AIST STP2 and ADP2 processes
Click here for the AIST STP2 and ADP2 layer definition files.
|adp.ldf||Layer info for AIST ADP Process (10kA/cm2)||18 February 2014|
|adp_fast.ldf||Layer info for AIST ADP Process (10kA/cm2)||18 February 2014|
|stp_nores.ldf||Layer info for AIST STP2 Process (2.5kA/cm2)||9 November 2015|
|stp_nores_fast.ldf||Layer info for AIST STP2 Process (2.5kA/cm2)||23 November 2015|
|stp_nores_med.ldf||Layer info for AIST STP2 Process (2.5kA/cm2)||23 November 2015|
|stp_res.ldf||Layer info for AIST STP2 Process (2.5kA/cm2)||9 November 2015|
Journal publications about InductEx, or with results generated by InductEx, are listed below. Copyright remains with the respective journals. Final preprints (as accepted) can be downloaded directly.
Stellenbosch University publications about InductEx
Collaborative publications that use or reference InductEx
Other publications that use or reference InductEx
This page hosts free software tools in a convenient repository.
JSIM and JSIM_n: console applications for Josephson circuit simulation. Fast and light-weight.
JSIM and the noise-enabled JSIM_n are ubiquitous Josephson circuit simulators; faster than Spice with inherent support for the Josephson junction.
The source code with makefile is included as a tar.gz archive, and is easy to build on Linux and Mac platforms.
The original paper on JSIM is also included because it is very difficult to find. It should be referenced as: E. S. Fang and T. Van Duzer, “A Josephson integrated circuit simulator (JSIM) for superconductive electronics application,” in Extended Abstracts of 1989 Intl. Superconductivity Electronics Conf. (ISEC ’89), Tokyo, Japan: JSAP, 1989, pp. 407-410.
|Windows executables for JSIM and JSIM_n||122.02 KB|
|JSIM user manual from Savoie University. (c) Pascal Febvre.||866.23 KB|
|JSIM_n source code, last modified by Mark Volkmann, 2014||124.15 KB|
|Original JSIM paper in Extended Abstracts of ISEC’89, by Emerson Fang||124.15 KB|
This page links to cell library repositories.
The FLUXONICS cell library houses GDS layout files, JSIM netlists, InductEx extraction batch files and more for every cell.
An experimental RSFQ cell library for the MITLL SFQ5ee process contains cells with integrated PTL drivers and receivers.
This page contains the links to open-source repositories for superconducting EDA modules.
TimEx is a netlist-to-Verilog HDL extraction module that finds timing parameters of SFQ circuits. The GitHub repository is https://github.com/sunmagnetics/TimEx
TimEx development was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office grant W911NF-17-1-0120.
JoSIM is an open-source simulation engine for superconducting circuits. It combines the functionality of JSIM and WRSpice. The GitHub repository is https://github.com/JoeyDelp/JoSIM
JoSIM development was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), via the U.S. Army Research Office grant W911NF-17-1-0120.
AUTO is a suite of modules for SFQ circuit margin and yield analysis and optimization. The GitHub repository is https://github.com/coldlogix/auto
AUTO was developed primarily by Thomas Ortlepp at Ilmenau University of Technology.