# Define and inspect an LDF fabrication process

Separate layout layer numbers, stack order, physical dimensions, material properties and result units using a complete three-layer teaching example.

## Compatibility

8 beta/preview

Published guidance with release-applicability limits. Confirm package applicability before following this guide.

**KB-GUI-005 · supported path**: Retain the specific annotation-alias warnings and check the process and terminal declarations. Do not change physical inputs merely to clear a warning; this mismatch does not invalidate every extraction.

**KB-GUI-006 · verified workaround**: Save work and close other saved tabs before exit when the intended Studio project must return as active. The checked single-tab restart does not repair multi-tab selection.

**KB-GUI-008 · verified workaround**: After a source edit, save the intended inputs, choose Run again and verify the new result. An earlier Completed label may still refer to the previous generation.

[Download Complete inline MQS microstrip inputs (ZIP)](/_functions/kbExample?name=inductex-inline-microstrip.zip)

Includes: strip.ixi, process.ldf, strip.cir, README.txt.

## Before starting

Use the fabrication owner’s approved process for real devices. The complete example below is a public microstrip teaching stack. Download its shared three-file example or use the inline-geometry guide for the matching IXI and circuit files. Do not substitute this stack for a protected or calibrated process.

## Steps

1. Open process.ldf in Studio. Review its source and process inspection view. Save an editable working copy and identify its process revision before changes.
2. Set Units for geometry and thickness, then define Parameters and Layer records using name = value and $End. An open legacy-format LDF can omit a header; do not invent protected-file metadata.
3. Keep Number (layout layer ID), Name (logical material) and Order (vertical construction order) distinct. Here M0 is number 17/order 0, I0 is number 2/order 1 and M1 is number 5/order 2.
4. Review thickness, mask polarity and material type for every layer. Review penetration depth and height-filament settings for the superconducting conductors.
5. Return to strip.ixi, check its Process reference and run that project. A syntactically valid LDF or a nominal stack drawing does not prove the intended physical model.

![The native LDF editor shows the M0, I0 and M1 teaching-stack records with layer numbers, order, thickness, mask, material type and penetration depth.](https://static.wixstatic.com/media/31de30_b7f0cf2eade14dbaa47a6638b2492658~mv2.png)

The actual LDF source shows the three stack records. The process panel is closed in this source illustration; it is not a rendered or extracted stack result.

## Complete process.ldf

```text
* Public microstrip teaching stack; dimensions use Units below
$Parameters
  Units = 1e-6
  SegmentSize = 2.0
  AbsMin = 0.025
  GPOverhang = 5.0
  ProcessHasGroundPlane = TRUE
  GPLayer = 17
  TermLayer = 19
  TextLayer = 18
  HFilaments = 1
  TerminalInRange = 1.0
  UnitL = 1
$End
$Layer
  Number = 17
  Name = M0
  Thickness = 0.2
  Lambda = 0.09
  Order = 0
  Mask = -1
  Filmtype = S
  HFilaments = 2
$End
$Layer
  Number = 2
  Name = I0
  Thickness = 0.15
  Order = 1
  Mask = -1
  Filmtype = I
$End
$Layer
  Number = 5
  Name = M1
  Thickness = 0.25
  Lambda = 0.09
  Order = 2
  Mask = 1
  Filmtype = S
  HFilaments = 3
$End
```

## Understand this stack

Units = 1e-6 makes one coordinate/thickness unit equal to 1 µm. Nominal unetched stack positions are M0 from 0 to 0.20 µm, I0 from 0.20 to 0.35 µm and M1 from 0.35 to 0.60 µm. The production editor’s nominal process snapshot reproduces these positions; it is not an etched-layout cross-section.

Filmtype S describes the superconductors; I describes the insulator. Lambda = 0.09 means 0.09 µm in this process. Material properties must come from the actual process, with temperature/frequency/model assumptions reviewed for the intended analysis.

M0 uses a negative mask and the declared ground-plane layer; GPOverhang bounds the generated ground region around the conductor model. M1 uses a positive mask. TermLayer = 19 and TextLayer = 18 identify annotation layers rather than deposited films.

SegmentSize and HFilaments control different mesh dimensions. Halving the planar segment size is a refinement change, not a process calibration or a guarantee of accuracy.

## Coordinate units and result units

Changing Units changes the physical sizes represented by the same coordinate and thickness numbers. UnitL instead normalizes inductance values and design values. Do not use one as a substitute for the other.

In the checked example UnitL = 1 uses henries and L1 1 2 3.9e-12. Setting UnitL = 1e-12 and the design value to 3.9 gives the same physical result displayed as 3.896479063 pH. Change the design-value convention consistently with the result-unit convention.

## Check the result

The checked 100 × 10 µm example gives L1 = 3.896479063e-12 H (3.896479063 pH), approximately 0.09028% below its 3.9 pH design value. Its mesh bytes and extracted value match the maintained GDS microstrip. This comparison is specific to these exact inputs and runtime.

Verify the intended ground plane, material layers, terminals and current-run units before comparing numbers. Use a justified refinement plan for real structures.

The detailed current CLI output/elements.txt contains the value quoted above in the configured UnitL units. The human-readable summary rounds this example to 3.89648 pH. Match units and printed precision before treating different displays as a numerical change.

## If the problem remains

The production editor rejects a Layer record missing required Thickness in this teaching stack; restore the real value before proceeding. The CLI rejects the missing process and undefined material-layer cases and recovers after correction.

The current candidate can flag TERM/TEXT with IXI_CROSS_UNKNOWN_LAYER even though these annotation aliases are accepted by the checked Core run and resolved to TermLayer/TextLayer. This focused mismatch is tracked as KB-GUI-005. Check the actual alias and declared layer numbers; do not rename conductor layers or ignore unrelated warnings.

Keep protected files intact. Obtain the correct process revision, access and validity from the issuer when required; editing metadata or copying an unrelated LDF does not repair a missing fabrication model.

## Actual Studio unit-change check

The native scenario saved UnitL = 1e-12 in the real process editor and changed the netlist design value to 3.9. The next normal GUI run showed Inductance [pH] with L1 = 3.89648. Restoring both conventions returned the original result and exact original input bytes.

![With UnitL 1e-12 and a matching design value of 3.9, the current native raw table reports Inductance in pH and extracted L1 of 3.89648.](https://static.wixstatic.com/media/31de30_86a83147d221474889752527723c3ac5~mv2.png)

The actual current GUI table uses pH after both the result-unit and design-value conventions were changed consistently. This is the same physical strip.

## Sources and verification details

Recorded inputs/builds only. Complete walkthrough and final-package acceptance remain separate.

- VAL-020: Windows catalog InductEx 8.0.1 (2 November 2026) and its bundled TTH 1.1.50; not final-package acceptance. Complete inline MQS strip, byte-identical mesh and identical inductance versus the maintained GDS example, length/display-unit changes, one mesh refinement and missing-process/port/layer rejection and recovery Sixteen bounded CLI checks. One refinement observation is not a convergence threshold. Design agreement is not physical calibration or solver/fit residual acceptance. Native GUI authoring, cancellation/retry, restart and final distributed-package checks remain pending.
- VAL-021: Frozen current Windows Studio editor/nominal-process analysis source, 3 November 2026. Seventeen production-parser/analysis checks: exact input syntax, three-layer nominal stack/units, malformed input and restoration, plus focused reproduction of TERM/TEXT annotation alias warnings This route is editor analysis only. It does not construct the Core model, run an extraction, verify physical calibration or complete a native GUI walkthrough. The accepted .end directive still receives an editor warning (KB-EDITOR-001); annotation alias warnings remain KB-GUI-005.
- VAL-023: Frozen Windows Studio source candidate with normal Core 8.0.1 dispatch, 3 November 2026; not a final distributed package. Normal production source edits/Undo/Redo/Save, licensed baseline/length/unit runs, port failure and correction, Stop/retry and a separate-process single-tab restart/rerun. File/directory selection used predetermined paths at the production dialog boundary Eighteen independent checks cover these stated routes. The prior Completed label after a saved source edit remains KB-GUI-008; stale-state acceptance is not passed. A Cancelled receipt retained an L1 row and is not accepted as a completed solve. Physical pickers, complete GUI article, final distributed package, other platforms, physical accuracy and mesh convergence remain pending. KB-GUI-006 single-tab restart workaround remains separate.

- studio-ldf-process-source: Current Windows Studio source, native authoring illustration, 3 November 2026. Authoring illustration only; no GUI extraction or complete walkthrough is shown. CLI/editor results are recorded separately. Annotation alias and .end warnings remain under review.
- studio-inline-picohenry-result: Frozen Windows Studio source candidate, actual native workflow, 3 November 2026. This image shows the stated recorded control/result only. The retained Completed-after-edit observation remains open; a Cancelled receipt is not accepted numerical success. Complete GUI article and final-package checks remain pending.

- inductex:docs/manual/ix_ldf.tex: Open process structure, global/layer parameters, physical and result units
- inductex:docs/manual/ix_layoutinput.tex: STRUCT coordinate-unit boundary and process reference
- inductex:docs/manual/studio_projects.tex: Inspect companion files and run the IXI project
- validation:inductex-inputs-windows-20261103: VAL-020 licensed CLI and VAL-021 separate editor-analysis checks; exact scope retained
- capture:studio-inputs-20261103T163127: Native authoring illustration only; exact reviewed input and image bytes
- validation:studio-inputs-native-windows-20261103: VAL-023; actual native edits, numerical runs, port recovery, Stop/retry and separate-process single-tab restart; provenance limitation retained

- The five cited maintained references still match their reviewed inventory hashes; existing source baselines were preserved.
- VAL-023 adds eighteen independent native checks. The saved-source completion label is an open provenance observation (KB-GUI-008); the actual Cancelled verdict is kept distinct from retained numerical rows. Original input bytes were restored.
- VAL-020 CLI and VAL-021 editor analysis remain separate from the later normal native workflow. Complete physical pickers, article/release acceptance and numerical qualification remain pending.

## Related guides

- [Export LDF layer mappings as InductEx-LVS™ technology JSON](/knowledge-base/inductex-convert-technology)
- [Create parameterised IXI geometry without a GDS file](/knowledge-base/inductex-ixi-geometry)
- [Build the circuit netlist required for extraction](/knowledge-base/inductex-netlist-build)
- [Define layout ports and match them to the circuit](/knowledge-base/inductex-port-design)
- [An IXI project cannot find an input file](/knowledge-base/inductex-missing-input)
- [Results still says Completed after I edit an IXI file](/knowledge-base/inductex-completed-after-edit)
- [Use a protected process file and diagnose access failures](/knowledge-base/inductex-protected-process)