# An extracted resistance or inductance looks unphysical

Check agreement between the circuit model and layout, port orientation, coupling and solution quality before accepting the extracted element values.

## Compatibility

8 interpretation; legacy support example

Published guidance with release-applicability limits. Confirm package applicability before following this guide.

## Check what the fitted model represents

The extracted branch values are fitted to the specified circuit model. A missing branch contribution or mutual coupling can force an otherwise useful field solution into an inadequate lumped model. A negative value is not automatically a harmless numerical artifact.

A historical support case attributed a negative resistance to an incomplete bias-network model. That diagnosis does not establish the cause of a new negative value.

## Review the result

1. Check port directions and the intended circuit topology against the physical layout.
2. Include the branch and coupling contributions required by that model; avoid changing physical parameters merely to make a value positive.
3. Inspect SVD rank, unknown count, condition number and residuals using the matching manual. A small voltage residual alone does not prove every element value is accurate.
4. Repeat a controlled mesh/refinement check and compare a simpler model before trusting the result.

## When to escalate

Provide a minimal model and the relevant solution diagnostics privately. Treat unexpected values as unresolved until the circuit and field model explain them.

## Compare with the design

Aim for low reported relative error in the model fit. The owner has not specified a new numerical cutoff for SVD or GMRES residuals.

For a meaningful nonzero design inductance, use 100 × abs(L_extracted − L_design) / abs(L_design) to compare the values. The general design target is below 10% deviation; below 5% is preferred.

Design agreement, model-fit residuals and solver convergence answer different questions. Check the physical model and refinement behaviour as well; these percentages are not universal solver-error or regression tolerances.

## Sources and verification details

Recorded inputs/builds only. Complete walkthrough and final-package acceptance remain separate.



- support:SUP-008: Generalised editorial finding; outcome qualification retained
- inductex:docs/manual/ix_output.tex: Quality of the singular value decomposition
- inductex:docs/manual/ix_netlist.tex: Circuit netlist
- owner:technical-review-20261102: Owner guidance on low relative error and design-inductance agreement

- The owner accepted the modelling explanation on 2 November 2026. Applicable release/platform and unrecorded walkthrough checks remain pending.

## Related guides

- [Why are series components reported together with ++ or --?](/knowledge-base/inductex-merged-series-values)
- [Check mesh convergence when a run is slow or results change](/knowledge-base/inductex-mesh-convergence)